The invention generally relates to a method for changing the configuration of a programmable logic module, a method for adapting a control device comprising a programmable logic module set up to execute a regulating function, and to a programming apparatus for writing to a programmable logic module.
In many fields of technology, control devices are used to regulate a physical process, a microcontroller of the control device cyclically executing a program which comprises determining new measured values from one or more sensors and actuating one or more actuators on the basis of a comparison of the measured values with desired values. In order to speed up the design of new control devices or regulating algorithms, placement on an existing control device is often carried out in this case and only individual (sub)functions are replaced. This procedure which is also known under the term bypassing can either be completely implemented on the existing control device (internal bypassing) or can resort to a separate Rapid Control Prototyping system (abbreviated to RCP system) in order to call the new function(s), the so-called bypass functions (external bypassing). Individual functions can be expediently replaced by adapting jump instructions.
EP 2869145 A1 discloses a method for influencing a control program of a control device, the control program comprising a multiplicity of first functions, at least one of which is designed to control an actuator, and a memory being provided, said memory having memory areas occupied by subroutines assigned to the first functions. The control program is in the form of a binary program code, the program code of the control program containing a jump address when called by one of the first functions, which jump address points to a memory address of the subroutine associated with the function call, and the subroutine being in the form of a sequence of binary program code, and a return instruction being present at the end of the sequence of the program code of the subroutine. The program code of the control program is examined for the occurrence of function calls and the jump addresses associated with the function calls and addresses of the return instructions are determined, the memory areas of the memory which are occupied by the respective subroutines being determined from the determination of the size. The designators which are assigned to the first functions and have sizes associated with the respective first functions and addresses of the memory areas are displayed in a display unit which is designed as part of a computer system. The computer system is used to select at least one of the first functions to be deleted, the size and address of the selected first function being stored in a function structure and at least one function call of the selected first function being deactivated and/or the first function being replaced with a second function by overwriting the program code of the selected first function with the program code of the second function.
Programmable logic modules known under the term Field Programmable Gate Array (abbreviated to FPGA) are increasingly being used to simulate and regulate systems with a high dynamic response, which logic modules also reliably regulate rapidly variable sections by use of parallel processing and a logic circuit that is tailored to the respective application. Since no sequential execution is carried out, unlike in microprocessors, and since no jump instructions are present, no bypassing has hitherto been able to be carried out for the regulating functions implemented on an FPGA. Another disadvantage of using FPGAs is that minor adaptations to the individual logic functions are possible only to a limited extent since the circuit has to be completely resynthesized in each case, which is time-consuming, in particular on account of the optimization of placement and routing. It would therefore be desirable to provide a simple way of adapting logic functions for programmable logic modules as well.
Partial reconfiguration is a procedure which is known from U.S. Pat. No. 7,902,866 B2, for example, for being able to change the configuration of an FPGA subsequently or at the runtime. In preparation for this, the FPGA configuration must already be divided into partitions in the design phase, in which case a first and a second partition, for example, are therefore created. Logic functions which are unalterable or are always present are provided in the first partition. The second partition is then a delimited area for which partial resynthesis and partial reconfiguration are possible, with the result that, in principle, the logic functions arranged in the second partition can be changed.
However, this procedure has a number of disadvantages. The partition interfaces must already be planned and firmly implemented in the initial design. Irrespective of the functionality or logic function implemented in the second partition, a fixed number of logic units and connection elements is reserved. As a result of the therefore necessary reservation of the greatest assumed number of required logic elements, resources remain unused in many cases. All logic functions arranged in the first partition remain firm; even when the currently implemented functionality of the second partition does not need them, there is still a space and energy requirement of the functions.
In order to design and process an FPGA configuration, “Torc: Towards an Open Source Tool Flow”, Proceedings of the 19th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2011, by N. Steiner et al. was presented. The Steiner reference discloses reading and writing a logic description in the form of an unmapped or mapped netlist. In light of Steiner, R. K. Soni et al. describe in “Open-Source Bitstream Generation”, 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines 2013, a possible way of making quick modifications to a bit stream which describes an FPGA configuration. A library of micro bit streams each describing individual basic units can be used to add further logic elements to an existing configuration on the basis of a mapped netlist.
“RapidSmith: Do-it-Yourself CAD Tools for Xilinx FPGAs”, 2011 21st International Conference on Field Programmable Logic and Applications, by C. Lavin et al. discloses a further design tool for FPGA configurations. In light of the Lavin reference, the paper “Rapid Post-Map Insertion of Embedded Logic Analyzers for Xilinx FPGAs”, 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines 2014, by B. L. Hutchings and J. Keeley describes a possible way of modifying an existing FPGA configuration without the need to recompile or resynthesize the complete circuit. Measuring circuits can therefore be subsequently introduced into an FPGA configuration which is otherwise unchanged by using previously unused logic elements or areas of the FPGA. Individual logic functions are not adapted and the values or signals which are output are therefore not changed.